Serial Binary Adder

I. Intended Learning Objectives
At the end of the tutorial, the readers should be able to: 1. Explain the operation of a serial binary adder 2. Construct the digital circuit using CircuitSim for a serial binary adder; and, 3. Perform simulation of the operation of a serial binary adder

II. Requirements
The readers should have a desktop PC or laptop (Win 7, 8, or 10) with an installed CircuitSim simulator to be able to effectively learn the concepts and procedures that will be discussed in this tutorial. Readers will be able to download a copy of the app at ra4king.github.io/CircuitSim/ download page or visit its official Github repository at ra4king/CircuitSim.

III. Difficulty
Intermediate

IV. Introduction to Serial Addition
Digital computers mostly done in parallel because this is a faster mode of operation. Serial operations are slower but require less equipment. To be able to demonstrate serial mode of operation, we will design a serial adder. Two set of shift register is used to store the serially add two binary number. Bits are added one pair at a time, sequentially , through a full adder (FA) circuit. The carry out of a full adder is transmitted to a D flip-Flop. The output of the flip-flop is then used as input carry for the next pair of significant bits. The two shift register are shifted to the right for a word-time period. The sum bits from the S output of a full adder could be transferred to a third shift register. By shifting the sum into A while the bits of A is shifted out. The serial input (SI) of register B is able to receive a new binary while the addend bits are shifted. Figure 1: Conceptual Block Digram The operation of a serial adder can be sum up by the conceptual block diagram shown in figure 1. Initially, both register A and B holds the addend , and the carry flip-flop is clear to 0. The serial output (SO) of A and B provide a pair of significant bit for the full adder (FA) at x and y. Output Q of the flip-flop gives the input carry at z. The shift-right control enables both registers and carry flip-flop; so at the clock pulse change, both registers are shifted once to the right, the sum bit from S enters the leftmost flip-flop of A, and the output carry is transferred into flip-flop Q. For this tutorial, we will create three separate circuit of shift register, full adder and the serial adder. The serial adder circuit is where we combined the configured shift register and full adder to perform the serial addition operation.

IV. Introduction to Serial Addition

Digital computers mostly done in parallel because this is a faster mode of operation. Serial operations are slower but require less equipment. To be able to demonstrate serial mode of operation, we will design a serial adder.

Two set of shift register is used to store the serially add two binary number. Bits are added one pair at a time, sequentially , through a full adder (FA) circuit. The carry out of a full adder is transmitted to a D flip-Flop. The output of the flip-flop is then used as input carry for the next pair of significant bits. The two shift register are shifted to the right for a word-time period. The sum bits from the S output of a full adder could be transferred to a third shift register. By shifting the sum into A while the bits of A is shifted out. The serial input (SI) of register B is able to receive a new binary while the addend bits are shifted.

Figure 1: Conceptual Block Digram

The operation of a serial adder can be sum up by the conceptual block diagram shown in figure 1. Initially, both register A and B holds the addend , and the carry flip-flop is clear to 0. The serial output (SO) of A and B provide a pair of significant bit for the full adder (FA) at x and y. Output Q of the flip-flop gives the input carry at z. The shift-right control enables both registers and carry flip-flop; so at the clock pulse change, both registers are shifted once to the right, the sum bit from S enters the leftmost flip-flop of A, and the output carry is transferred into flip-flop Q.

For this tutorial, we will create three separate circuit of shift register, full adder and the serial adder. The serial adder circuit is where we combined the configured shift register and full adder to perform the serial addition operation.

V. Serial Adder circuit implementation on CircuitSim
We have discussed earlier the operation and the conceptual block diagram by which it operates in a manner that the The serial output (SO) of A and B provide a pair of significant bit for the full adder (FA) at x and y. Output Q of the flip-flop gives the input carry at z. We will begin constructing the shift register circuit where the primary bit addend is given. The 4 bit shift register is constructed by connecting a cascaded D flip-flop by which the leftmost flipflop is feed by a serial input. The succeeding flip-flops are then connected to the output of the prior flip-flop until the last configured flip-flop where the serial output is presented. This flip-flops are connected in a one clock pulse. The shift register terminals should be labeled as SI, SO, and CP for the serial input, output and clock pulse. You can browse my last tutorial about shift register in full detail discussion. Now, we open a new circuit to create the serial binary adder which was discussed earlier. This comprises two set of serial input, a full adder and d flip-flop. We select two set shift register to serve as the serial input addend processor. We labeled the two shift register as A and B. The serial output of this two set of register is feed to the x and y terminal of the full adder, labeled as FA. The full adder component can be selected from the arithmetic tab on the component library. We add a D flip-flop to serve as a memory element that establish the carry in to the full adder. Connect the Q terminal of the D flip-flop to the carry in of the full adder. At the same time, connect D terminal to the output terminal of the adder. We add input and output component including the clock pulse. For the clock pulse of D flip-flop, the clock pulse input is connected to an AND gate together with the shift-right input before feed to the CP terminal of the D flip-flop. This is to ensure to control the operation of the d flip-flop that it will only activate when a logic 1 is applied thru it. At the same time, connect the input element shift-right and clock pulse to the shift register A's serial input (SI) and clock pulse (CP) terminal, respectively. The shift register input is feed by a separate input element, but the clock pulse terminal is connected to the same clock as to shift register A. The output of the full adder is then connected to a output element to display the serial output sum of both serial input. Initially, both register A and B holds a 0 addend when the shift-right still at logic-0, and the same goes for the carry flip-flop . As shift -right and external input is activate to logic 1, the serial output (SO) of A and B provide a pair of 1 bit for the full adder (FA) at x and y equal to 1. Output Q of the flip-flop gives the input carry at 1. So at the clock pulse change, both registers are shifted once to the right, the sum bit from S enters the leftmost flip-flop of A, and the output carry is transferred into flip-flop Q. You should observe in the serial output a change of logic value from 1 to 0 as clock pulse tick.

V. Serial Adder circuit implementation on CircuitSim

We have discussed earlier the operation and the conceptual block diagram by which it operates in a manner that the The serial output (SO) of A and B provide a pair of significant bit for the full adder (FA) at x and y. Output Q of the flip-flop gives the input carry at z. We will begin constructing the shift register circuit where the primary bit addend is given. The 4 bit shift register is constructed by connecting a cascaded D flip-flop by which the leftmost flipflop is feed by a serial input. The succeeding flip-flops are then connected to the output of the prior flip-flop until the last configured flip-flop where the serial output is presented. This flip-flops are connected in a one clock pulse. The shift register terminals should be labeled as SI, SO, and CP for the serial input, output and clock pulse. You can browse my last tutorial about shift register in full detail discussion.

Now, we open a new circuit to create the serial binary adder which was discussed earlier. This comprises two set of serial input, a full adder and d flip-flop. We select two set shift register to serve as the serial input addend processor. We labeled the two shift register as A and B. The serial output of this two set of register is feed to the x and y terminal of the full adder, labeled as FA. The full adder component can be selected from the arithmetic tab on the component library.

We add a D flip-flop to serve as a memory element that establish the carry in to the full adder. Connect the Q terminal of the D flip-flop to the carry in of the full adder. At the same time, connect D terminal to the output terminal of the adder.

We add input and output component including the clock pulse. For the clock pulse of D flip-flop, the clock pulse input is connected to an AND gate together with the shift-right input before feed to the CP terminal of the D flip-flop. This is to ensure to control the operation of the d flip-flop that it will only activate when a logic 1 is applied thru it. At the same time, connect the input element shift-right and clock pulse to the shift register A's serial input (SI) and clock pulse (CP) terminal, respectively. The shift register input is feed by a separate input element, but the clock pulse terminal is connected to the same clock as to shift register A. The output of the full adder is then connected to a output element to display the serial output sum of both serial input.

Initially, both register A and B holds a 0 addend when the shift-right still at logic-0, and the same goes for the carry flip-flop . As shift -right and external input is activate to logic 1, the serial output (SO) of A and B provide a pair of 1 bit for the full adder (FA) at x and y equal to 1. Output Q of the flip-flop gives the input carry at 1. So at the clock pulse change, both registers are shifted once to the right, the sum bit from S enters the leftmost flip-flop of A, and the output carry is transferred into flip-flop Q. You should observe in the serial output a change of logic value from 1 to 0 as clock pulse tick.

VI. Simulation of the Shift Register
We have now created the a serial binary adder by combining a shift register, full addder and a D flip-flop. To start the simulation, simply click simulation > simulation enable and also clock enable. In the running simulation as shown, we can observe a different bit value stored on D Flip-Flop. In the simulation we start by setting the values of the input to 1. As shift -right and external input is activate to logic 1, the serial output (SO) of A and B provide a pair of 1 bit for the full adder (FA) at x and y equal to 1. Output Q of the flip-flop gives the input carry at 1. You can see the recorded simulation on the video below.

VI. Simulation of the Shift Register

We have now created the a serial binary adder by combining a shift register, full addder and a D flip-flop. To start the simulation, simply click simulation > simulation enable and also clock enable. In the running simulation as shown, we can observe a different bit value stored on D Flip-Flop. In the simulation we start by setting the values of the input to 1. As shift -right and external input is activate to logic 1, the serial output (SO) of A and B provide a pair of 1 bit for the full adder (FA) at x and y equal to 1. Output Q of the flip-flop gives the input carry at 1. You can see the recorded simulation on the video below.

VIII. Summary
In this tutorial, we start by understanding the operation of a serial addition. By incorporating a shift register with an arithmetic operator and memory latch, in full adder and D flip-flop respectively, we are able to perform serial addition. The serial output (SO) of both shift register provide a pair of significant bit for the full adder (FA) at x and y. Output Q of the flip-flop gives the input carry at z. The shift-right control enables both registers and carry flip-flop. So, at a 0 logic at the shift-right input, the serial addition functionality is disabled. In addition, we can observe on the simulations that the shifting of the serial output at the full adder reaches the exact value of the internal input as the shift is terminates. It goes the same with a 0 logic at the said input. The shifts in the value of the sum is displayed and can be observed on the D flip-flop, which serves as the memory element.

VIII. Summary

In this tutorial, we start by understanding the operation of a serial addition. By incorporating a shift register with an arithmetic operator and memory latch, in full adder and D flip-flop respectively, we are able to perform serial addition. The serial output (SO) of both shift register provide a pair of significant bit for the full adder (FA) at x and y. Output Q of the flip-flop gives the input carry at z. The shift-right control enables both registers and carry flip-flop. So, at a 0 logic at the shift-right input, the serial addition functionality is disabled. In addition, we can observe on the simulations that the shifting of the serial output at the full adder reaches the exact value of the internal input as the shift is terminates. It goes the same with a 0 logic at the said input. The shifts in the value of the sum is displayed and can be observed on the D flip-flop, which serves as the memory element.

VIII. Reference
- Conceptual Reference: Morris Mano, Digital Design, 3rd Edition - Image and Video Source: All videos and images use in this tutorial is recorded and captured by the author. Otherwise, it is specified in the text.

IX. Curriculum
You can browse my other tutorial for digital circuits implemented using CircuitSim from the following links bellow. 1. Binary Ripple Counter 2. Shift Register

Posted on Utopian.io - Rewarding Open Source Contributors

Congratulations! This post has been upvoted from the communal account, @minnowsupport, by juecoree from the Minnow Support Project. It's a witness project run by aggroed, ausbitbank, teamsteem, theprophet0, someguy123, neoxian, followbtcnews, and netuoso. The goal is to help Steemit grow by supporting Minnows. Please find us at the Peace, Abundance, and Liberty Network (PALnet) Discord Channel. It's a completely public and open space to all members of the Steemit community who voluntarily choose to be there.

If you would like to delegate to the Minnow Support Project you can do so by clicking on the following links: 50SP, 100SP, 250SP, 500SP, 1000SP, 5000SP.
Be sure to leave at least 50SP undelegated on your account.

Sort:

Trending

[-]

portugalcoin (76) 8 years ago

Thank you for the contribution. It has been approved.

The tutorial looks pretty dense. Try to use the < br> tag between images and texts. Also putting paragraphs helped a lot. However I really liked the format of your tutorial. Good job.

You can contact us on Discord.
[utopian-moderator]

$0.87

1 vote

utopian.tip (46) 8 years ago

Hey @portugalcoin, I just gave you a tip for your hard work on moderation. Upvote this comment to support the utopian moderators and increase your future rewards!

$0.00

juecoree (72) 8 years ago

Thank you, @portugalcoin. I am trying to find ways to retain my formating but make not dense. I have used the
tag but i think it does not work well with tables. Thanks for the tips!

portugalcoin (76) 8 years ago (edited)

Try to put this way between the rows of the table.
Example:

<table>
  <tr>
    <td>Info 1</td>
  </tr>
 <tr>
    <td><br></td>
  </tr>
  <tr>
    <td>Info 2</td>
  </tr>
</table>

Thank you! I would try this in my next tutorial. I would need to read more about the table html tag, and also the table markdown. It is of great help.

minnowsupport (71) 8 years ago

utopian-io (71) 8 years ago

Hey @juecoree I am @utopian-io. I have just upvoted you!

Achievements

You have less than 500 followers. Just gave you a gift to help you succeed!
Seems like you contribute quite often. AMAZING!

Community-Driven Witness!

I am the first and only Steem Community-Driven Witness. Participate on Discord. Lets GROW TOGETHER!

Vote for my Witness With SteemConnect
Proxy vote to Utopian Witness with SteemConnect
Or vote/proxy on Steemit Witnesses

Up-vote this comment to grow my power and help Open Source contributions like this one. Want to chat? Join me on Discord https://discord.gg/Pc8HG9x